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1 ltc1909-8 19098f features applicatio s u descriptio u typical applicatio u wide operating range, no r sense tm step-down dc/dc controller with smbus programming n smbus/i 2 c tm programmable output voltage: 1.3v to 3.5v n no sense resistor required n 2% to 90% duty cycle at 200khz n t on(min) 100ns n true current mode control n stable with ceramic c out n power good output voltage monitor and 50 m s timer n wide v in range: 4v to 36v (abs max) n precision resistor divider and reference provide 1.35% output voltage accuracy over temperature n adjustable switching frequency and current limit n forced continuous control pin n programmable soft-start n output overvoltage protection n optional short-circuit shutdown timer n available in a 28-lead ssop package n power supplies for dsps, asics, fpgas and cpus n voltage margining the ltc ? 1909-8 is a synchronous step-down switching regulator controller with a digitally programmable output voltage. the output voltage is selected from one of two 5-bit settings programmed into internal registers via a 2-wire smbus/i 2 c interface. the interface features safe- guards against invalid output voltages and allows the mi- croprocessor to turn the regulator on and off. valley cur- rent control delivers very low duty cycles without requiring a sense resistor. operating frequency is selected by an external resistor and is compensated for variations in v in and v out . discontinuous mode operation provides high efficiency operation at light loads. a forced continuous control pin reduces noise and rf interference and can assist second- ary winding regulation by disabling discontinuous mode operation when the main output is lightly loaded. fault protection is provided by internal foldback current limiting, an output overvoltage comparator and optional short-circuit shutdown timer. the ltc1909-8 is available in the 28-lead ssop package. , ltc and lt are registered trademarks of linear technology corporation. no r sense is a trademark of linear technology corporation. i 2 c is a trademark of philips electronics n.v. figure 1. high efficiency step-down converter 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 run/ss v on pgood v rng fcb i th sgnd i on v fb sel sda scl vron pgtmr boost tg sw sense + pgnd bg intv cc v in extv cc v cc gnd fb v osense cpuon 470pf sel sda scl vron 100pf 0.1 f 100k 20k 39k 100k 100k 11k 1 r on 1.4m 1% c in : united chemicon thcr60e1h106tz c out1, 2 : cornell dubilier esre181me04b/ panasonic eefveog181r d1: diodes inc. b340a l1: sumida cep125-1r8mc-h m1: si4884 m2: si4874 0.22 f cmdsh-3 0.1 f ltc1909-8 4.7 f 6.3v m2 d1 19098 f01 + c out1, 2 180 f 4v 2 c out3 22 f 6.3v x7r + m1 v in 5v to 24v v out 2.5v or 2.6v 10a (v out set by sel) gnd gnd c in 10 f 50v 4 l1 1.8 h 5v ext
2 ltc1909-8 19098f (note 1) input supply voltage v in , i on ..................................................C 0.3v to 36v boosted topside driver supply voltage boost .................................................. C 0.3v to 42v sw, sense + voltages ................................. C 5v to 36v extv cc , (boost C sw), run/ss, pgood, intv cc , sel, sda, scl, vron, pgtmr, v osense , fb, cpuon, v cc voltages .......................... C 0.3v to 7v fcb, v on , v rng voltages ....... C 0.3v to (intv cc + 0.3v) i th , v fb voltages...................................... C 0.3v to 2.7v tg, bg, intv cc , extv cc peak currents .................... 2a tg, bg, intv cc , extv cc rms currents .............. 50ma operating ambient temperature range ltc1909-8eg (note 2) ....................... C 40 c to 85 c junction temperature (note 4) ............................ 125 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number ltc1909-8eg t jmax = 125 c, q ja = 95 c/ w (switching regulator controller) the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v in = 15v unless otherwise noted. absolute axi u rati gs w ww u package/order i for atio uu w electrical characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view g package 28-lead plastic ssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 run/ss v on pgood v rng fcb i th sgnd i on v fb sel sda scl vron pgtmr boost tg sw sense + pgnd bg intv cc v in extv cc v cc gnd fb v osense cpuon consult ltc marketing for parts specified with wider operating temperature ranges. symbol parameter conditions min typ max units main control loop i q input dc supply current normal 900 2000 m a shutdown supply current 15 30 m a v fb feedback reference voltage i th = 1.2v (note 3) l 0.792 0.800 0.808 v d v fb(linereg) feedback voltage line regulation v in = 4v to 30v, i th = 1.2v (note 3) 0.002 %/v d v fb(loadreg) feedback voltage load regulation i th = 0.5v to 1.9v (note 3) l C 0.05 C 0.3 % i fb feedback input current v fb = 0.8v C5 50 na g m(ea) error amplifier transconductance i th = 1.2v (note 3) l 1.4 1.7 2 ms v fcb forced continuous threshold l 0.76 0.8 0.84 v i fcb forced continuous pin current v fcb = 0.8v C 1 C 2 m a t on on-time i on = 60 m a, v on = 1.5v 212 250 288 ns i on = 30 m a, v on = 1.5v 425 500 575 ns t on(min) minimum on-time i on = 180 m a, v on = 0v 50 100 ns t off(min) minimum off-time i on = 60 m a, v on = 1.5v 250 400 ns v sense(max) maximum current sense threshold v rng = 1v, v fb = 0.76v 113 133 153 mv v pgnd C v sense + v rng = 0v, v fb = 0.76v l 79 93 107 mv v rng = intv cc , v fb = 0.76v 158 186 214 mv v sense(min) minimum current sense threshold v rng = 1v, v fb = 0.84v C 67 mv v pgnd C v sense + v rng = 0v, v fb = 0.84v C 47 mv v rng = intv cc , v fb = 0.84v C 93 mv d v fb(ov) output overvoltage fault threshold 5.5 7.5 9.5 %
3 ltc1909-8 19098f (switching regulator controller) the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v in = 15v unless otherwise noted. electrical characteristics (smbus vid programmer) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. 2.7v v cc 5.5v (note 5) unless otherwise stated. symbol parameter conditions min typ max units v cc operating supply voltage range 2.7 5.5 v i cc supply current cpuon, pgtmr pins are open l 350 m a r fb-sense resistance between v osense and fb l 14 20 26 k w de divider error (note 6) v osense programmed from 1.3v to 3.5v l C 0.35 0.35 % v ih scl, sda input high voltage l 2.1 v v il scl, sda input low voltage l 0.8 v v ih sel, vron input high voltage 1.3 2 v v il sel, vron input low voltage l 0.8 1.3 v v hyst sel, vron hysteresis 50 mv v ol sda, cpuon pgtmr output low voltage i = 3ma l 0.4 v i in scl, sda, sel, vron input current sda not acknowledging, 0 v pin 5.5v, l 10 m a v pin = 5.5v for vron only symbol parameter conditions min typ max units d v fb(uv) output undervoltage fault threshold 520 600 680 mv v run/ss(on) run pin start threshold l 0.8 1.5 2 v v run/ss(le) run pin latchoff enable threshold run/ss pin rising 4 4.5 v v run/ss(lt) run pin latchoff threshold run/ss pin falling 3.5 4.2 v i run/ss(c) soft-start charge current v run/ss = 0v C 0.5 C 1.2 C 3 m a i run/ss(d) soft-start discharge current v run/ss = 4.5v, v fb = 0v 0.8 1.8 3 m a v in(uvlo) undervoltage lockout v in falling l 3.4 3.9 v v in(uvlor) undervoltage lockout release v in rising l 3.5 4 v tg r up tg driver pull-up on resistance tg high 2 3 w tg r down tg driver pull-down on resistance tg low 2 3 w bg r up bg driver pull-up on resistance bg high 3 4 w bg r down bg driver pull-down on resistance bg low 1 2 w tg t r tg rise time c load = 3300pf, 20% to 80% of swing 20 ns tg t f tg fall time c load = 3300pf, 20% to 80% of swing 20 ns bg t r bg rise time c load = 3300pf, 20% to 80% of swing 20 ns bg t f bg fall time c load = 3300pf, 20% to 80% of swing 20 ns internal v cc regulator v intvcc internal v cc voltage 6v < v in < 30v, v extvcc = 4v l 4.7 5 5.3 v d v ldo(loadreg) internal v cc load regulation i cc = 0ma to 20ma, v extvcc = 4v C 0.1 2% v extvcc extv cc switchover voltage i cc = 20ma, v extvcc rising l 4.5 4.7 v d v extvcc extv cc switch drop voltage i cc = 20ma, v extvcc = 5v 150 300 mv d v extvcc(hys) extv cc switchover hysteresis 200 mv pgood output d v fbh pgood upper threshold v fb rising 5.5 7.5 9.5 % d v fbl pgood lower threshold v fb falling C 5.5 C 7.5 C 9.5 % d v fb(hys) pgood hysteresis v fb returning 1 2 % v pgl pgood low voltage i pgood = 5ma 0.15 0.4 v
4 ltc1909-8 19098f (smbus vid programmer) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. 2.7v v cc 5.5v (note 5) unless otherwise stated. electrical characteristics note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: the ltc1909-8e is guaranteed to meet performance specifications from 0 c to 70 c. specifications over the C40 c to 85 c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 3: the ltc1909-8 is tested in a feedback loop that adjusts v fb to achieve a specified error amplifier output voltage (i th ). note 4: t j is calculated from the ambient temperature t a and power dissipation p d as follows: ltc1909-8e: t j = t a + (p d ? 130 c/w) note 5: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to device ground unless otherwise noted. note 6: the divider error is tested in a feedback loop that adjusts fb to 0.8v for each 5-bit code. note 7: these parameters are guaranteed by design and are not tested in production. smbus timing is referenced to v il and v ih levels. note 8: dominated by the switching regulator. the delay due to the smbus vid programmer is only 500ns typ. note 9: measured from the rising edge of sda during data high acknowledgment. symbol parameter conditions min typ max units i sk1 sda, pgtmr, cpuon 0 v pin 2.7v l 51960 ma sink current at v cc = 2.7v i sk2 sda, pgtmr, cpuon 0 v pin 5.5v l 35 65 150 ma sink current at v cc = 5.5v i lkg pgtmr, cpuon leakage current 0 v pin 5.5v 0.2 m a i pu vron pull-up current v pin = 0 l C1 C 2.5 C 7 m a timing (note 7) f smb smbus operating frequency l 10 100 khz t buf bus free time between stop/start l 4.7 m s t hd:sta hold time after (repeated) start l 4 m s t su:sta repeated start setup time l 4.7 m s t su:sto stop condition setup time l 4 m s t hd:dat data hold time l 300 ns t su:dat data setup time l 250 ns t low clock low period l 4.7 m s t high clock high period l 4 m s t f scl, sda fall time 0.9v cc to 0.65v l 300 ns t r scl, sda rise time 0.65v to 2.25v l 1000 ns t ssh sel to v osense high (note 8) toggle sel to switch from 01111b to 10000b, l 500 ns v fb = 0.8v t ssl sel to v osense low (note 8) toggle sel to switch from 10000b to 01111b, l 500 ns v fb = 0.8v t spl sel toggling to pgtmr low toggle sel to select new code l 160 500 ns c l = 100pf, 10k w pull-up, s2 in test circuit t ph stop bit to cpuon high (note 9) c l = 100pf, 10k w pull-up, s2 in test circuit l 2 m s t pl stop bit to cpuon low (note 9) c l = 0.1 m f, 10k w pull-up, s1 in test circuit l 20 50 m s t ppl stop bit to pgtmr low (note 9) c l = 100pf, 10k w pull-up, s2 in test circuit l 250 ns t vh vron high to cpuon high c l = 100pf, 10k w pull-up, s2 in test circuit l 2 m s t vl vron low to cpuon low c l = 0.1 m f, 10k w pull-up, s1 in test circuit l 50 m s t vpl vron low to pgtmr low c l = 100pf, 10k w pull-up, s2 in test circuit l 130 500 ns t pgl pgtmr low duration c l = 100pf, 10k w pull-up, s2 in test circuit 30 50 70 m s
5 ltc1909-8 19098f typical perfor a ce characteristics uw load current (a) 0.001 efficiency (%) 70 80 10 19098 g18 60 50 0.01 0.1 1 100 90 discontinuous mode continuous mode v in = 10v v out = 2.5v extv cc = 5v figure 1 circuit efficiency vs load current efficiency vs input voltage input voltage (v) 0 80 efficiency (%) 85 90 95 100 5101520 19098 g19 25 30 i load = 1a i load = 10a fcb = 5v figure 1 circuit frequency vs input voltage input voltage (v) 5 frequency (khz) 240 260 25 19098 g20 220 200 10 15 20 300 280 i out = 10a fcb = 0v figure 1 circuit i out = 0a load regulation load current (a) 0 ? v out (%) 0.2 0.1 8 19098 g21 0.3 0.4 2 4 6 10 0 figure 1 circuit i th voltage vs load current load current (a) 0 i th voltage (v) 1.0 1.5 19098 g22 0.5 0 5 10 15 2.5 2.0 continuous mode discontinuous mode figure 1 circuit current sense threshold vs i th voltage i th voltage (v) 0 200 current sense threshold (mv) 100 0 100 200 300 0.5 1.0 1.5 2.0 19098 g23 2.5 3.0 1v 0.7v 0.5v 1.4v v rng = 2v current limit foldback v fb (v) 0 0 maximum current sense threshold (mv) 25 50 75 100 125 150 0.2 0.4 0.6 0.8 1778 g09 transient response (discontinuous mode) transient response v out 50mv/div i l 5a/div 20 m s 19098 g16 load step 0a to 10a v in = 15v v out = 2.5v fcb = 0v figure 1 circuit v out 50mv/div i l 5a/div 20 m s 19098 g17 load step 1a to 10a v in = 15v v out = 2.5v fcb = intv cc figure 1 circuit
6 ltc1909-8 19098f typical perfor a ce characteristics uw maximum current sense threshold vs temperature maximum current sense threshold vs v rng voltage feedback reference voltage vs temperature error amplifier g m vs temperature extv cc switch resistance vs temperature fcb pin current vs temperature run/ss pin current vs temperature run/ss latchoff thresholds vs temperature undervoltage lockout threshold vs temperature v rng voltage (v) 0.5 0 maximum current sense threshold (mv) 50 100 150 200 300 0.75 1.0 1.25 1.5 19098 g25 1.75 2.0 250 temperature ( c) 50 ?5 100 maximum current sense threshold (mv) 120 150 0 50 75 19098 g25 110 140 130 25 100 125 v rng = 1v temperature ( c) ?0 0.78 feedback reference voltage (v) 0.79 0.80 0.81 0.82 25 0 25 50 19098 g27 75 100 125 temperature ( c) 50 ?5 1.0 g m (ms) 1.4 2.0 0 50 75 19098 g28 1.2 1.8 1.6 25 100 125 temperature ( c) 50 ?5 0 extv cc switch resistance ( ) 4 10 0 50 75 19098 g29 2 8 6 25 100 125 temperature ( c) ?0 fcb pin current ( a) 0.50 0.25 0 25 75 19098 g30 0.75 1.00 ?5 0 50 100 125 1.25 1.50 temperature ( c) 50 ?5 ? fcb pin current ( a) 0 3 0 50 75 19098 g31 ? 2 1 25 100 125 pull-up current pull-down current temperature ( c) ?0 3.0 run/ss threshold (v) 3.5 4.0 4.5 5.0 25 0 25 50 19098 g32 75 100 125 latchoff enable latchoff threshold temperature (c) ?0 2.0 undervoltage lockout threshold (v) 2.5 3.0 3.5 4.0 25 0 25 50 19098 g33 75 100 125
7 ltc1909-8 19098f typical perfor a ce characteristics uw resistance between v osense and fb pins vs temperature v cc supply current vs supply voltage v cc (v) 1.5 v cc supply current ( a) 19098 g01 350 300 250 200 150 100 50 0 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 t a = 25 c v cc supply current vs temperature temperature ( c) v cc supply current ( a) 19098 g02 300 250 200 150 100 50 0 ?5 ?5 ?5 5 25 45 65 85 105 125 v cc = 5.5v v cc = 2.7v temperature ( c) r sense (k ) 19098 g03 20.08 20.06 20.04 20.02 20.00 19.98 19.96 19.94 19.92 19.90 19.88 ?5 ?5 ?5 5 25 45 65 85 105 125 v cc = 2.7v to 5.5v scl, sda, sel and vron hysteresis vs temperature scl, sda, sel and vron input high and low voltage vs temperature scl, sda, sel and vron input high and low voltage vs supply voltage temperature ( c) input high and low voltage (v) 19098 g04 1.40 1.35 1.30 1.25 1.20 1.15 1.10 ?5 ?5 ?5 5 25 45 65 85 105 125 input high, v cc = 5.5v input low, v cc = 5.5v input high, v cc = 2.7v input low, v cc = 2.7v supply voltage (v) input high and low voltage (v) 19098 g05 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 input high t a = 25 c input low temperature ( c) hysteresis (v) 19098 g06 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 ?5 ?5 ?5 5 25 45 65 85 105 125 v cc = 5.5v v cc = 2.7v scl, sda, sel input current vs temperature scl, sda, sel and vron hysteresis vs supply voltage sda, cpuon, pgtmr output low voltage vs temperature temperature ( c) output low voltage (v) 19098 g08 0.25 0.20 0.15 0.10 0.05 0 ?5 ?5 ?5 5 25 45 65 85 105 125 v cc = 2.7v i pin = 3ma v cc = 5.5v temperature ( c) input current (na) 19098 g09 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ?5 ?5 ?5 5 25 45 65 85 105 125 scl pin sel pin sda pin v cc = 5.5v v pin = 5.5v (smbus vid programmer) supply voltage (v) hysteresis (v) 19098 g07 0.10 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 t a = 25 c
8 ltc1909-8 19098f typical perfor a ce characteristics uw vron pull-up current vs temperature (smbus vid programmer) pgtmr, cpuon leakage current vs temperature sda, pgtmr, cpuon sink current vs temperature temperature ( c) sink current (ma) 19098 g10 80 70 60 50 40 30 20 10 0 ?5 ?5 ?5 5 25 45 65 85 105 125 v cc = 5.5v, i sk2 v cc = 2.7v, i sk1 temperature ( c) leakage current (na) 19098 g11 7 6 5 4 3 2 1 0 ?0 ?0 ?0 0 20 40 60 80 100 120 v pin = 5.5v temperature ( c) vron pull-up current ( a) 19098 g12 2.50 2.45 2.40 2.35 2.30 2.25 2.20 2.15 2.10 2.05 2.00 1.95 1.90 ?5 ?5 ?5 5 25 45 65 85 105 125 v cc = 5.5v v cc = 2.7v resistor divider error vs temperature power good timer low duration vs temperature vron pull-up current vs supply voltage supply voltage (v) 1.5 ? vron pull-up current ? ( a) 19098 g013 3.0 2.5 2.0 1.5 1.0 0.5 0 2.5 3.5 4.5 5.5 6.5 t a = 25 c v ron = 0v temperature ( c) power good timer low duration ( s) 19098 g14 52.0 51.5 51.0 50.5 50.0 49.5 49.0 ?0 ?0 ?0 0 20 40 60 80 100 120 v cc = 5.5v v cc = 2.7v temperature ( c) divider error (%) 19098 g15 0.25 0.20 0.15 0.10 0.05 0 0.05 0.10 0.15 0.20 ?5 35 ?5 5 25 45 65 85 105 125 v cc = 2.7v (minimum v cc ) code 15 code 31 code 0 code 16
9 ltc1909-8 19098f uu u pi fu ctio s run/ss (pin 1): run control and soft-start input. a capacitor to ground at this pin sets the ramp time to full output current (approximately 3s/ m f) and the time delay for overcurrent latchoff (see applications information). forcing this pin below 0.8v shuts down the device. v on (pin 2): on-time voltage input. voltage trip point for the on-time comparator. tying this pin to the output voltage makes the on-time proportional to v out . the comparator input defaults to 0.7v when the pin is grounded and 2.4v when the pin is tied to intv cc . pgood (pin 3): power good output. open-drain logic output that is pulled to ground when the output voltage is not within 7.5% of the regulation point. v rng (pin 4): sense voltage range input. the voltage at this pin is ten times the nominal sense voltage at maxi- mum output current and can be set from 0.5v to 2v by a resistive divider from intv cc . the nominal sense voltage defaults to 70mv when this pin is tied to ground, 140mv when tied to intv cc . fcb (pin 5): forced continuous input. tie this pin to ground to force continuous synchronous operation at low load, to intv cc to enable discontinuous mode operation at low load or to a resistive divider from a secondary output when using a secondary winding. i th (pin 6): current control threshold and error amplifier compensation point. the current comparator threshold increases with this control voltage. the voltage ranges from 0v to 2.4v with 0.8v corresponding to zero sense voltage (zero current). sgnd (pin 7): signal ground. all small-signal compo- nents and compensation components should connect to this ground, which in turn connects to pgnd at one point. i on (pin 8): on-time current input. tie a resistor from v in to this pin to set the one-shot timer current and thereby set the switching frequency. v fb (pin 9): error amplifier feedback input. this pin connects to the error amplifier input to the center tap of the smbus programmable divider at the fb pin (pin 17). sel (pin 10): register select input. a ttl compatible logic input pin that is used to select 1 of 2 resistor divider settings. sel selects the setting in register 0 if pulled low and the setting in register 1 if pulled high. sda (pin 11): smbus data input/output. sda is a high impedance input when address, command or data bits are shifted into the smbus interface. it is an open-drain n-channel output when acknowledging or sending data back to the microprocessor during read back. it requires a pull-up resistor or current source to v cc . scl (pin 12): smbus clock input. data at the sda pin is latched into the ltc1909-8 smbus interface at the rising edge of the clock and is shifted out of the sda pin at the falling edge of the clock. scl is a high impedance input pin. it is driven by the open collector output of a micropro- cessor and requires a pull-up resistor or current source to v cc . vron (pin 13): global control input. this ttl compatible input pin is pulled up internally by a 2.5 m a current source. pulling vron low forces the open-drain output pins (cpuon and pgtmr) to pull to ground. if the ltc1909-8 is programmed to turn on a dc/dc converter, pulling vron high three-states the cpuon pin and allows the switching regulator to soft-start if cpuon is tied to the run/ss pin. pgtmr (pin 14): power good timer output. this open- drain output is pulled low for 50 m s each time the switching regulator is turned on or sel is toggled to select a new code. pgtmr may be connected to the fcb pin to force the converter into continuous mode operation. this reduces the time needed for the converter output to settle to a lower output voltage under light load conditions if the sel pin is toggled to select a lower output voltage. cpuon (pin 15): cpu dc/dc converter control. open- drain output, usually connected to the run/ss pin. it pulls low to shut down the converter or becomes high imped- ance to allow the converter to soft-start. v osense (pin 16): sense input. upper terminal of the smbus programmable resistor divider that is connected directly to the regulated output voltage node.
10 ltc1909-8 19098f uu u pi fu ctio s fb (pin 17): feedback input. center tap of the smbus programmable divider that is connected to pin 9. gnd (pin 18): smbus programmer ground. connect to regulator signal ground at pin 7. v cc (pin 19): positive supply of the smbus vid program- mer. 2.7v v cc 5.5v. may be connected to the intv cc pin. bypass this pin to ground with a 0.1 m f ceramic capacitor if using an external supply. extv cc (pin 20): external v cc input. when extv cc ex- ceeds 4.7v, an internal switch connects this pin to intv cc and shuts down the internal regulator so that controller and gate drive power is drawn from extv cc . do not exceed 7v at this pin and ensure that extv cc < v in . v in (pin 21): main input supply. decouple this pin to pgnd with an rc filter (1 w , 0.1 m f). intv cc (pin 22): internal 5v regulator output. the driver and control circuits are powered from this voltage. de- couple this pin to power ground with a minimum of 4.7 m f low esr tantalum or other low esr capacitor. the internal 5v regulator is shut down when v run/ss <1.5v. bg (pin 23): bottom gate drive. drives the gate of the bottom n-channel mosfet between ground and intv cc . pgnd (pin 24): power ground. connect this pin closely to the source of the bottom n-channel mosfet, the (C) terminal of c vcc and the (C) terminal of c in . sense + (pin 25): current sense comparator input. the (+) input to the current comparator is normally connected to the sw pin unless using a sense resistor (see applica- tions information). sw (pin 26): switch node. the (C) terminal of the boot- strap capacitor c b connects here. this pin swings from a diode voltage drop below ground up to v in . tg (pin 27): top gate drive. drives the top n-channel mosfet with a voltage swing equal to intv cc superim- posed on the switch node voltage sw. boost (pin 28): boosted floating driver supply. the (+) terminal of the bootstrap capacitor c b connects here. this pin swings from a diode voltage drop below intv cc up to v in + intv cc . test circuit + cpuon or pgtmr fb v osense vron gnd 19098 tc sel sda scl v cc vron sel sda scl v cc 10k s1 5v 0.1 f s2 0.8v 100pf smbus vid programmer test circuit
11 ltc1909-8 19098f fu ctio al diagra u u w 1.4v 0.7v v rng 4 + + + + + + 8 i on v on 0.7v 2.4v 2 ost 5 14 fcb pgtmr* smbon* dcon* 20 extv cc 21 v in 1 a r on v von i ion t on = (10pf) r sq 20k i cmp i rev q6 1v 3.3 a shdn switch logic bg on fcnt f 0.8v + 4.7v ov 1 240k q1 q2 q3 0.8v 0.6v 0.6v i th r c c c1 ea ss 0.8v q4 + + 4 q5 6 run/ss *part of the smbus vid programmer c ss 1 cpuon* 15 19098 fd sgnd r fb1 * 7 9 run shdn 23 pgnd 24 pgood v fb 19 v cc * 17 fb* 18 gnd* 10 sel* 12 scl* sda* 16 v osense * intv cc 22 sw 26 sense + 25 tg c b v in c in 27 boost 28 + + uv 0.76v ov 0.84v c vcc v out m2 m1 l1 c out r fb2 * 1.3v + 0.8v ref 5v reg + 13 + 1.2 a 6v d b i thb 1 3 por* 10:5 mux* smbus interface* register 0* register 1* on/off state machine* dcon* smbon* vron* v cc * 1.3v * * * * 50 s timer* 11
12 ltc1909-8 19098f ti i g diagra s w u w slave address command code data low data high 1 1 scl sda 11 1 xxxxx xxx xxx r/w ack vid4 vid3 vid0 vid2 vid1 c7 c6 c5 000 23456789 10111213141516171819202122232425262728293031323334353637 p s r/w ack vid4 vid3 vid0 vid2 vid1 ack vid4 vid3 vid0 vid1 vid2 ack ack slave address slave address command code data low data high 1 1 scl sda note 1: s = start condition, p = stop condition note 2: c7, c6, c5 = 001 for setup, 010 for read-back, 000 for on and 011 for off 19098 td01 11 1 xxxxx ack c7 c6 c5 000 1 1 r/w 11000 0 0 23456789 101112131415161718 smbus write word protocol, with smbus address = 1110001b, command byte = 001xxxxb, data low = 01001xxxb, data high = 01011xxxb smbus read word protocol, with smbus address = 1110001b, command byte = 010xxxxb, data low = 01001000b, data high = 01011000b 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 p s ack s vid4 vid3 vid0 vid1 vid2 ack dcon 0 0 dcon ack operating sequence
13 ltc1909-8 19098f ti i g diagra s w u w t buf t low t high t r t f t hd:sta t hd:dat sda scl t su:dat t su:sta t su:sto stop 19098 td02 start start stop t hd:sta 19098 td03 t ph t spl t vl t ssh t pl t ppl t vpl t pgl t vh t ssl 90% 10% note: timing relative to the stop bit (p) is measured from the rising edge of sda see table 1 for v min and v max sense voltages t pgl t pgl scl p stop 2nd on protocol 2nd off protocol smbon dcon vron cpu_on v osense (v ref = 0.8v) sel sda pgtmr p 1.3v 1.3v 1.3v 1.3v 0.7v v max v min 0v 0v timing for smbus interface vron, sel, cpuon and pgtmr timing
14 ltc1909-8 19098f operatio u the ltc1909-8 consists of two independent sections: a current mode controller for the dc/dc step-down con- verter and a smbus vid voltage programmer. it simplifies the design of smbus controlled power supplies. current mode controller in normal operation, the top mosfet of the current mode controller is turned on for a fixed interval determined by a one-shot timer ost. when the top mosfet is turned off, the bottom mosfet is turned on until the current com- parator i cmp trips, restarting the one-shot timer and initi- ating the next cycle. inductor current is determined by sensing the voltage between the pgnd and sense + pins using either the bottom mosfet on-resistance or a sepa- rate sense resistor. the voltage on the i th pin sets the comparator threshold corresponding to inductor valley current. the error amplifier ea adjusts this voltage by comparing the feedback signal v fb from the output voltage with an internal 0.8v reference. the feedback voltage is derived from the output voltage by a resistive divider in the smbus vid programmer. if the load current increases, it causes a drop in the feedback voltage relative to the reference. the i th voltage then rises until the average inductor current again matches the load current. at low load currents, the inductor current can drop to zero and become negative. this is detected by current reversal comparator i rev which then shuts off m2, resulting in discontinuous operation. both switches will remain off with the output capacitor supplying the load current until the i th voltage rises above the zero current level (0.8v) to initiate another cycle. discontinuous mode operation is disabled by comparator f when the fcb pin is brought below 0.8v, forcing continuous synchronous operation. the operating frequency is determined implicitly by the top mosfet on-time and the duty cycle required to maintain regulation. the one-shot timer generates an on- time that is proportional to the ideal duty cycle, thus holding frequency approximately constant with changes in v in . the nominal frequency can be adjusted with an external resistor r on . overvoltage and undervoltage comparators ov and uv pull the pgood output low if the output feedback voltage exits a 7.5% window around the regulation point. fur- thermore, in an overvoltage condition, m1 is turned off and m2 is turned on and held on until the overvoltage condition clears. foldback current limiting is provided if the output is shorted to ground. as v fb drops, the buffered current threshold voltage i thb is pulled down by clamp q3 to a 1v level set by q4 and q6. this reduces the inductor valley current level to one sixth of its maximum value as v fb approaches 0v. pulling the run/ss pin low forces the controller into its shutdown state, turning off both m1 and m2. releasing the pin allows an internal 1.2 m a current source to charge up an external soft-start capacitor c ss . when this voltage reaches 1.5v, the controller turns on and begins switch- ing, but with the i th voltage clamped at approximately 0.6v below the run/ss voltage. as c ss continues to charge, the soft-start current limit is removed. shorting the run/ss pin to the cpuon pin of the smbus vid programmer puts the regulator under software control. the open-drain cpuon pin does not interfere with the soft-start cycle. intv cc /extv cc power power for the top and bottom mosfet drivers and most of the internal controller circuitry is derived from the intv cc pin. the top mosfet driver is powered from a floating bootstrap capacitor c b . this capacitor is re- charged from intv cc through an external schottky diode d b when the top mosfet is turned off. when the extv cc pin is grounded and v run/ss >1.5v, an internal 5v low dropout regulator supplies the intv cc power from v in . if extv cc rises above 4.7v, the internal regulator is turned off, and an internal switch connects extv cc to intv cc . this allows a high efficiency source connected to extv cc , such as an external 5v supply or a secondary output from the converter, to provide the intv cc power. voltages up to 7v can be applied to extv cc for additional gate drive. if the input voltage is low and intv cc drops below 3.5v, undervoltage lockout circuitry prevents the power switches from turning on. smbus vid voltage programmer the smbus interface is used to program the divider (to set the output voltage of the dc/dc converter) and to shut down the current mode controller or allow it to soft-start. (refer to functional diagram)
15 ltc1909-8 19098f it uses two pins, scl and sda to communicate with a master device through the read word and write word protocols. the v il and v ih logic threshold voltages of the sda and scl pins are 0.8v and 2.1v respectively, which comply with rev 1.1 version of the intel system manage- ment bus specifications. both pins require a resistor or active pull-up (see the ltc1694 data sheet) to v cc . data is clocked out of the sda pin at the falling edge and latched in at the rising edge of the scl clock signal. the slave address of the interface for both read and write protocols is fixed at e2h. there are three types of write word protocols: setup, on and off and one read word protocol called read-back. the setup write word protocol is used to set up two internal 5-bit registers (register 0 and register 1) with alternate resistor divider dac settings. the on and off write word protocols do not modify register contents but are used to shutdown the converter or to allow it to soft- start. the read word protocol is used to verify the contents of the registers as well as to check whether the converter is operating or in shutdown from a status bit (dcon). table 3 in the applications information section shows the data bits that identify each protocol as setup, on, off or read-back. controller control the vid programmer provides the vron and cpuon pins for the purpose of shutting down or allowing the converter to soft-start. cpuon is an open-drain, n-channel output pin that is normally tied to the run/ss pin of the controller along with its soft-start capacitor. if the n-channel is turned off, the pin enters a high impedance state and the capacitor is allowed to charge up and soft-start the converter. when shutting down the converter, the n-channel fet at the cpuon pin will typically discharge a 0.1 m f soft-start ca- pacitor from 3v to 0.35v in 21 m s with v cc = 2.7v. on power-up, the power-on reset (por) circuit in the smbus vid programmer turns on the n-channel to shut down the converter. the cpuon pin can also be controlled to clear overcurrent faults in the switching regulator (see soft- start and latchoff with the run/ss pin section). the cpuon pin is under the control of an internal on/off state machine that is accessed using the smbus on/off write word protocols and the vron pin. the vron pin operatio u (refer to functional diagram) has a trip point of 1.3v with 50mv of hysteresis. it is ttl compatible and has a 2.5 m a pull-up to v cc . pulling vron low will force cpuon low immediately, regardless of the on/off state machine. pulling vron high or allowing it to float high hands control to the on/off state machine. table 1 summarizes the function of the control pins. the smbon control bit is explained in the next section. table 1. dc/dc converter control pins vron smbon dcon pgtmr cpuon 0x 1 0 0 10 1 0 0 1 - 0 for 50 m s z (note 2) (note 1) - 1 0 for 50 m s z (note 2) (note 1) note 1: also triggered by sel pin toggling. note 2: z = high impedance the ltc1909-8 provides safeguards against incorrect di- vider codes and the unintentional turn-on or turn-off of the dc/dc converter. incorrect codes due to bus conflicts during setup protocols can cause damage to circuits pow- ered by the dc/dc converter. the safeguards built into the ltc1909-8 include read-back, repeated on and off pro- tocols, ignoring on protocols if the registers have not been set up (since power-up), locking out registers while the dc/dc converters are operating and latching in vid codes only in setup protocols. after power-up, the microprocessor must set up the reg- isters before the ltc1909-8 recognizes on protocols. this requirement ensures that the correct dc/dc converter out- put is programmed before the converters are turned on. after setup, read-back allows the contents of registers 0 and 1 to be verified in case the vid codes were corrupted by noise or bus conflicts. in order to turn on the dc/dc converter, two on protocols must be sent to slave address e2h without any other (e2h) protocols in between. protocols to other slave addresses are still allowed and are ignored. similarly, two off proto- cols must be sent to slave address e2h to turn the convert- ers off. the on and off protocols are monitored by an internal state machine. the output of the state machine, smbon, is high after two on commands and low after two off commands. repeated on and off protocols reduce the chances of bus conflicts and noise turning the converter
16 ltc1909-8 19098f on or off accidentally. in both on and off protocols, the ltc1909-8 does not latch in the data low and data high bytes. this protects the settings that have already been loaded into the registers and verified by read-back. once the converter is turned on (both smbon and vron are high) the contents of registers 0 and 1 are protected and can only be altered with setup protocols if vron is pulled low or two off protocols are sent to the ltc1909-8 (to force smbon low). during read-back, the microproces- sor can check the on or off state of the controller by testing the dcon status bit that follows each 5-bit code. this bit is low only when both smbon and vron are high. resistor divider the resistor divider settings comply with the intel desktop vrm8.4 vid specifications. the divider consists of a fixed 20k (typical) resistor, r fb1 , connected between the v osense and fb pins and a variable resistor, r fb2 , from fb to gnd. the fb pin is connected to the v fb pin of the step-down controller to set the output voltage of the converter. each resistor has a tolerance of 30% but the divider ratio is accurate to 0.35%. the error budget for the dc/dc con- verter output voltage must include the 0.35% ratio toler- ance and the 1% tolerance in the 0.8v reference. the output of the dc/dc converter is given by: v out = v ref ? (r fb2 + r fb1 )/r fb2 where v ref = 0.8v is the internal reference voltage of the converter. table 2 shows the 32 possible converter output voltages. the microprocessor controls the sel pin to se- lect the contents of one of the registers as the active divider setting. the sel pin has a trip point of 1.3v with 50mv of hysteresis and is ttl compatible. it controls an internal 10:5 digital multiplexer and selects the contents of register 0 when pulled low and register 1 when pulled high. when sel is toggled, and the new converter output is lower or greater by 7.5%, the overvoltage and undervoltage com- parators of the controller may trip causing the pgood pin of the controller to go low. this condition will recover automatically as the converter charges up the output or allows the output to drop to the new voltage setting. power good timer the pgtmr or power good timer pin is also an open- drain, n-channel output. it pulls low if the dc/dc converter operatio u (refer to functional diagram) table 2. dc/dc converter output voltage vid4 vid3 vid2 vid1 vid0 output voltage 0 0 0 0 0 2.05v 0 0 0 0 1 2.00v 0 0 0 1 0 1.95v 0 0 0 1 1 1.90v 0 0 1 0 0 1.85v 0 0 1 0 1 1.80v 0 0 1 1 0 1.75v 0 0 1 1 1 1.70v 0 1 0 0 0 1.65v 0 1 0 0 1 1.60v 0 1 0 1 0 1.55v 0 1 0 1 1 1.50v 0 1 1 0 0 1.45v 0 1 1 0 1 1.40v 0 1 1 1 0 1.35v 0 1 1 1 1 1.30v 1 0 0 0 0 3.50v 1 0 0 0 1 3.40v 1 0 0 1 0 3.30v 1 0 0 1 1 3.20v 1 0 1 0 0 3.10v 1 0 1 0 1 3.00v 1 0 1 1 0 2.90v 1 0 1 1 1 2.80v 1 1 0 0 0 2.70v 1 1 0 0 1 2.60v 1 1 0 1 0 2.50v 1 1 0 1 1 2.40v 1 1 1 0 0 2.30v 1 1 1 0 1 2.20v 1 1 1 1 0 2.10v 1 1 1 1 1 2.00v is in shutdown or on power-up. when the converter is turned on, an internal timer keeps pgtmr low for 50 m s (typical) which allows time for the converters to enter regu- lation. toggling the sel pin while the converter is turned on also causes the pgtmr pin to pull low for 50 m s. the pgtmr pin may be used to force continuous opera- tion in the dc/dc converter. if the sel pin is toggled to select a lower output voltage, if may take an unacceptably
17 ltc1909-8 19098f long time for the output of the dc/dc converter to de- crease to the new voltage under light load conditions. to reduce this time needed, the pgtmr pin can be connected to the fcb (force continuous bar) pin of the converter. when the sel pin is toggled to select a new code, the fcb pin is forced low for 50 m s. this forces the dc/dc converter out of burst mode tm operation and into continuous mode. the pgtmr pin may be tied to the same pull-up resistor as the pgood pin. smbus controller supply if the extv cc pin is tied to ground, the v cc pin of the smbus controller should be tied to an external 5v supply. it should not be tied to the intv cc pin because the internal 5v regulator at the intv cc pin is shut down while v run/ss is below 1.5v and the smbus controller will not be pow- ered up. if the extv cc pin is tied to an external 5v supply, operatio u (refer to functional diagram) the v cc pin can be tied to the same supply or to the intv cc pin since the intv cc pin is connected to the extv cc pin by an internal switch when v extvcc >4.7v. the extv cc and v cc voltages should be kept below the absolute maximum rating of 7v. power-up reset on power-up, the internal por circuit generates a low reset pulse, which stays low until v cc rises above approxi- mately 2.2v. the reset pulse forces the smbus interface into an idle state in which it listens for a start bit. at the same time the outputs of both register 0 and register 1 are set to 11111b. the dcon bit is pulled high so that the cpuon pin is pulled low to shut down the dc/dc con- verter. pgtmr is also pulled low as the converter is shut down and therefore not in regulation. burst mode is a trademark of linear technology corporation. applicatio s i for atio wu uu the basic ltc1909-8 application circuit is shown in figure 1. external component selection is primarily deter- mined by the maximum load current and begins with the selection of the sense resistance and power mosfet switches. the ltc1909-8 uses either an external sense resistor or the on-resistance of the synchronous power mosfet for determining the inductor current. the desired amount of ripple current and operating frequency largely determines the inductor value. finally, c in is selected for its ability to handle the large rms current into the con- verter and c out is chosen with low enough esr to meet the output voltage ripple and transient specification. maximum sense voltage and v rng pin inductor current is determined by measuring the voltage across a sense resistance that appears between the pgnd and sense + pins. the maximum sense voltage is set by the voltage applied to the v rng pin and is equal to approximately (0.133) ? v rng . the current mode control loop will not allow the inductor current valleys to exceed (0.133) ? v rng /r sense . in practice, one should allow some margin for variations in the ltc1909-8 and external com- ponent values and a good guide for selecting the sense resistance is: r v i sense rng out max = 10 () an external resistive divider from intv cc can be used to set the voltage of the v rng pin between 0.5v and 2v resulting in nominal sense voltages of 50mv to 200mv. additionally, the v rng pin can be tied to sgnd or intv cc in which case the nominal sense voltage defaults to 70mv or 140mv, respectively. the maximum allowed sense voltage is about 1.33 times this nominal value. connecting the sense + pin the ltc1909-8 can be used with or without a sense resistor. when using a sense resistor, it is placed between the source of the bottom mosfet m2 and ground. con- nect the sense + pin to the source of the bottom mosfet so that the resistor appears between the sense + and pgnd pins. using a sense resistor provides a well defined current limit, but adds cost and reduces efficiency. alter- natively, one can eliminate the sense resistor and use the bottom mosfet as the current sense element by simply connecting the sense + pin to the switch node sw at the drain of the bottom mosfet. this improves efficiency, but
18 ltc1909-8 19098f applicatio s i for atio wu uu one must carefully choose the mosfet on-resistance as discussed below. power mosfet selection the ltc1909-8 requires two external n-channel power mosfets, one for the top (main) switch and one for the bottom (synchronous) switch. important parameters for the power mosfets are the breakdown voltage v (br)dss , threshold voltage v (gs)th , on-resistance r ds(on) , reverse transfer capacitance c rss and maximum current i ds(max) . the gate drive voltage is set by the 5v intv cc supply. consequently, logic-level threshold mosfets must be used in ltc1909-8 applications. if the input voltage is expected to drop below 5v, then sub-logic level threshold mosfets should be considered. when the bottom mosfet is used as the current sense element, particular attention must be paid to its on- resistance. mosfet on-resistance is typically specified with a maximum value r ds(on)(max) at 25 c. in this case, additional margin is required to accommodate the rise in mosfet on-resistance with temperature: r r ds on max sense t ()( ) = r the r t term is a normalization factor (unity at 25 c) accounting for the significant variation in on-resistance with temperature, typically about 0.4%/ c as shown in figure 2. for a maximum temperature of 100 c, using a value r t = 1.3 is reasonable. the power dissipated by the top and bottom mosfets strongly depends upon their respective duty cycles and the load current. when the ltc1909-8 is operating in continuous mode, the duty cycles for the mosfets are: d v v d vv v top out in bot in out in = = the resulting power dissipation in the mosfets at maxi- mum output current are: p top = d top i out(max) 2 r t(top) r ds(on)(max) + k v in 2 i out(max) c rss f p bot = d bot i out(max) 2 r t(bot) r ds(on)(max) both mosfets have i 2 r losses and the top mosfet includes an additional term for transition losses, which are largest at high input voltages. the constant k = 1.7a C1 can be used to estimate the amount of transition loss. the bottom mosfet losses are greatest when the bottom duty cycle is near 100%, during a short-circuit or at high input voltage. operating frequency the choice of operating frequency is a tradeoff between efficiency and component size. low frequency operation improves efficiency by reducing mosfet switching losses but requires larger inductance and/or capacitance in order to maintain low output ripple voltage. the operating frequency of ltc1909-8 applications is determined implicitly by the one-shot timer that controls the on-time t on of the top mosfet switch. the on-time is set by the current into the i on pin according to: t v i pf on von ion = () 10 tying a resistor r on from v in to the i on pin yields an on- time inversely proportional to v in . for a step-down con verter, this results in approximately constant fre- quency operation as the input supply varies: junction temperature ( c) ?0 r t normalized on-resistance 1.0 1.5 150 19098 f02 0.5 0 0 50 100 2.0 figure 2. r ds(on) vs. temperature
19 ltc1909-8 19098f applicatio s i for atio wu uu f v vr pf hz out von on = [] () 10 to hold frequency constant during output voltage changes, tie the v on pin to v out . the v on pin has internal clamps that limit its input to the one-shot timer. if the pin is tied below 0.7v, the input to the one-shot is clamped at 0.7v. similarly, if the pin is tied above 2.4v, the input is clamped at 2.4v. because the voltage at the i on pin is about 0.7v, the current into this pin is not exactly inversely proportional to v in , especially in applications with lower input voltages. to correct for this error, an additional resistor r on2 connected from the i on pin to the 5v intv cc supply will further stabilize the frequency. r v v r on on 2 5 07 = . changes in the load current magnitude will also cause frequency shift. parasitic resistance in the mosfet switches and inductor reduce the effective voltage across the inductance, resulting in increased duty cycle as the load current increases. by lengthening the on-time slightly as current increases, constant frequency operation can be maintained. this is accomplished with a resistive divider from the i th pin to the v on pin and v out . the values required will depend on the parasitic resistances in the specific application. a good starting point is to feed about 25% of the voltage change at the i th pin to the v on pin as shown in figure 3a. place capacitance on the v on pin to filter out the i th variations at the switching frequency. the resistor load on i th reduces the dc gain of the error amp and degrades load regulation, which can be avoided by using the pnp emitter follower of figure 3b. inductor selection given the desired input and output voltages, the inductor value and operating frequency determine the ripple current: d= ? ? ? ? - ? ? ? ? i v fl v v l out out in 1 lower ripple current reduces core losses in the inductor, esr losses in the output capacitors and output voltage ripple. highest efficiency operation is obtained at low frequency with small ripple current. however, achieving this requires a large inductor. there is a tradeoff between component size, efficiency and operating frequency. a reasonable starting point is to choose a ripple current that is about 40% of i out(max) . the largest ripple current occurs at the highest v in . to guarantee that ripple current does not exceed a specified maximum, the inductance should be chosen according to: l v fi v v out l max out in max = d ? ? ? ? - ? ? ? ? () () 1 once the value for l is known, the type of inductor must be selected. high efficiency converters generally cannot af- ford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy or kool m m ? cores. a variety of inductors designed for high current, low voltage applications are available from manu- facturers such as sumida, panasonic, coiltronics, coil- craft and toko. figure 3. correcting frequency shift with load current changes c von 0.01 f r von2 100k r von1 30k r c c c v out v on ltc1909-8 (3a) i th c von 0.01 f r von2 10k r von1 3k r c 10k c c v out 19098 f03 intv cc v on ltc1909-8 (3b) i th 2n5087 kool m m is a registered trademark of magnetics, inc.
20 ltc1909-8 19098f schottky diode d1 selection the schottky diode d1 shown in figure 1 conducts during the dead time between the conduction of the power mosfet switches. it is intended to prevent the body diode of the bottom mosfet from turning on and storing charge during the dead time, which can cause a modest (about 1%) efficiency loss. the diode can be rated for about one half to one fifth of the full load current since it is on for only a fraction of the duty cycle. in order for the diode to be effective, the inductance between it and the bottom mosfet must be as small as possible, mandating that these components be placed adjacently. the diode can be omit- ted if the efficiency loss is tolerable. c in and c out selection the input capacitance c in is required to filter the square wave current at the drain of the top mosfet. use a low esr capacitor sized to handle the maximum rms current. ii v v v v rms out max out in in out @ () 1 this formula has a maximum at v in = 2v out , where i rms = i out(max) / 2. this simple worst-case condition is commonly used for design because even significant de- viations do not offer much relief. note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to derate the capacitor. the selection of c out is primarily determined by the esr required to minimize voltage ripple and load step transients. the output ripple d v out is approximately bounded by: dd + ? ? ? ? v i esr fc out l out 1 8 since d i l increases with input voltage, the output ripple is highest at maximum input voltage. typically, once the esr requirement is satisfied, the capacitance is adequate for filtering and has the necessary rms current rating. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. special polymer capacitors offer very low esr but have lower capacitance density than other types. tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. aluminum electrolytic capacitors have significantly higher esr, but can be used in cost-sensitive applications providing that consideration is given to ripple current ratings and long term reliability. ceramic capacitors have excellent low esr characteristics but can have a high voltage coefficient and audible piezoelectric effects. the high q of ceramic capacitors with trace inductance can also lead to signifi- cant ringing. when used as input capacitors, care must be taken to ensure that ringing from inrush currents and switching does not pose an overvoltage hazard to the power switches and controller. to dampen input voltage transients, add a small 5 m f to 50 m f aluminum electrolytic capacitor with an esr in the range of 0.5 w to 2 w . high performance through-hole capacitors may also be used, but an additional ceramic capacitor in parallel is recom- mended to reduce the effect of their lead inductance. top mosfet driver supply (c b , d b ) an external bootstrap capacitor c b connected to the boost pin supplies the gate drive voltage for the topside mosfet. this capacitor is charged through diode d b from intv cc when the switch node is low. when the top mosfet turns on, the switch node rises to v in and the boost pin rises to approximately v in + intv cc . the boost capacitor needs to store about 100 times the gate charge required by the top mosfet. in most applications a 0.1 m f to 0.47 m f x5r or x7r dielectric capacitor is adequate. discontinuous mode operation and fcb pin the fcb pin determines whether the bottom mosfet remains on when current reverses in the inductor. tying this pin above its 0.8v threshold enables discontinuous operation where the bottom mosfet turns off when inductor current reverses. the load current at which current reverses and discontinuous operation begins de- pends on the amplitude of the inductor ripple current and will vary with changes in v in . tying the fcb pin below the applicatio s i for atio wu uu
21 ltc1909-8 19098f 0.8v threshold forces continuous synchronous operation, allowing current to reverse at light loads and maintaining high frequency operation. in addition to providing a logic input to force continuous operation, the fcb pin provides a means to maintain a flyback winding output when the primary is operating in discontinuous mode. the secondary output v sec is nor- mally set as shown in figure 4 by the turns ratio n of the transformer. however, if the controller goes into discon- tinuous mode and halts switching due to a light primary load current, then v sec will droop. an external resistor divider from v sec to the fcb pin sets a minimum voltage v sec(min) below which continuous operation is forced until v sec has risen above its minimum. vv r r sec min () . =+ ? ? ? ? 08 1 4 3 fault conditions: current limit and foldback the maximum inductor current is inherently limited in a current mode controller by the maximum sense voltage. in the ltc1909-8, the maximum sense voltage is controlled by the voltage on the v rng pin. with valley current control, the maximum sense voltage and the sense resistance determine the maximum allowed inductor valley current. the corresponding output current limit is: i v r i limit sns max ds on t l =+d () () r 1 2 the current limit value should be checked to ensure that i limit(min) > i out(max) . the minimum value of current limit generally occurs with the largest v in at the highest ambi- ent temperature, conditions that cause the largest power loss in the converter. note that it is important to check for self-consistency between the assumed mosfet junction temperature and the resulting value of i limit which heats the mosfet switches. caution should be used when setting the current limit based upon the r ds(on) of the mosfets. the maximum current limit is determined by the minimum mosfet on- resistance. data sheets typically specify nominal and maximum values for r ds(on) , but not a minimum. a reasonable assumption is that the minimum r ds(on) lies the same amount below the typical value as the maximum lies above it. consult the mosfet manufacturer for further guidelines. to further limit current in the event of a short circuit to ground, the ltc1909-8 includes foldback current limiting. if the output falls by more than 25%, then the maximum sense voltage is progressively lowered to about one sixth of its full value. minimum off-time and dropout operation the minimum off-time t off(min) is the smallest amount of time that the ltc1909-8 is capable of turning on the bottom mosfet, tripping the current comparator and turning the mosfet back off. this time is generally about 300ns. the minimum off-time limit imposes a maximum duty cycle of t on /(t on + t off(min) ). if the maximum duty cycle is reached, due to a dropping input voltage for example, then the output will drop out of regulation. the minimum input voltage to avoid dropout is: vv tt t in min out on off min on () () = + intv cc regulator an internal p-channel low dropout regulator produces the 5v supply that powers the drivers and internal circuitry within the ltc1909-8. the intv cc pin can supply up to 50ma rms and must be bypassed to ground with a minimum of 4.7 m f tantalum or other low esr capacitor. good bypassing is necessary to supply the high transient applicatio s i for atio wu uu v in sense + ltc1909-8 sgnd fcb extv cc tg sw optional extv cc connection 5v < v sec < 7v r3 r4 19098 f04 t1 1:n bg pgnd + c sec 1 m f v out v sec v in + c in 1n4148 + c out figure 4. secondary output loop and extv cc connection
22 ltc1909-8 19098f currents required by the mosfet gate drivers. applica- tions using large mosfets with a high input voltage and high frequency of operation may cause the ltc1909-8 to exceed its maximum junction temperature rating or rms current rating. most of the supply current drives the mosfet gates unless an external extv cc source is used. in continuous mode operation, this current is i gatechg = f(q g(top) + q g(bot) ). the junction temperature can be estimated from the equations given in note 2 of the electrical characteristics. for example, the ltc1909-8 is limited to less than 14ma from a 30v supply: t j = 70 c + (14ma)(30v)(130 c/w) = 125 c for larger currents, consider using an external supply with the extv cc pin. extv cc connection the extv cc pin can be used to provide mosfet gate drive and control power from the output or another external source during normal operation. whenever the extv cc pin is above 4.7v the internal 5v regulator is shut off and an internal 50ma p-channel switch connects the extv cc pin to intv cc . intv cc power is supplied from extv cc until this pin drops below 4.5v. do not apply more than 7v to the extv cc pin and ensure that extv cc v in . the follow- ing list summarizes the possible connections for extv cc : 1. extv cc grounded. intv cc is always powered from the internal 5v regulator. 2. extv cc connected to an external supply. a high effi- ciency supply compatible with the mosfet gate drive requirements (typically 5v) can improve overall efficiency. 3. extv cc connected to an output derived boost network. the low voltage output can be boosted using a charge pump or flyback winding to greater than 4.7v. the system will start-up using the internal linear regulator until the boosted output supply is available. external gate drive buffers the ltc1909-8 drivers are adequate for driving up to about 30nc into mosfet switches with rms currents of 50ma. applications with larger mosfet switches or oper- ating at frequencies requiring greater rms currents will benefit from using external gate drive buffers such as the ltc1693. alternately, the external buffer circuit shown in figure 5 can be used. note that the bipolar devices reduce the signal swing at the mosfet gate and benefit from an increased extv cc voltage of about 6v. applicatio s i for atio wu uu figure 5. optional external gate driver q1 fmmt619 gate of m1 tg boost sw q2 fmmt720 q3 fmmt619 gate of m2 bg 10 19098 f05 intv cc pgnd q4 fmmt720 10 soft-start and latchoff with the run/ss pin the run/ss pin provides a means to shut down the ltc1909-8 as well as a timer for soft-start and overcurrent latchoff. pulling the run/ss pin below 0.8v puts the ltc1909-8 into a low quiescent current shutdown (i q < 30 m a). releasing the pin allows an internal 1.2 m a current source to charge up the external timing capacitor c ss . if run/ss has been pulled all the way to ground, there is a delay before starting of about: t v a csfc delay ss ss = m =m () 15 12 13 . . ./ when the voltage on run/ss reaches 1.5v, the ltc1909-8 begins operating with a clamp on i th of approximately 0.9v. as the run/ss voltage rises to 3v, the clamp on i th is raised until its full 2.4v range is available. this takes an additional 1.3s/ m f, during which the load current is folded back until the output reaches 75% of its final value. the pin can be driven from logic (figures 6a or 6b) or from the cpuon pin (figures 6c and 6d). diode d1 reduces the start delay while allowing c ss to charge up slowly for the soft- start function. after the controller has been started and given adequate time to charge up the output capacitor, c ss is used as a short-circuit timer. after the run/ss pin charges above 4v, if the output voltage falls below 75% of its regulated value, then a short-circuit fault is assumed. a 1.8 m a current then begins discharging c ss . if the fault condition persists until the run/ss pin drops to 3.5v, then the
23 ltc1909-8 19098f controller turns off both power mosfets, shutting down the converter permanently. the run/ss pin must be actively pulled down to ground in order to restart opera- tion. if the run/ss pin is tied to the cpuon pin, this is achieved by pulling the vron pin low or by sending two off protocols to the smbus vid programmer to force the cpuon pin low. the overcurrent protection timer requires that the soft- start timing capacitor c ss be made large enough to guar- antee that the output is in regulation by the time c ss has reached the 4v threshold. in general, this will depend upon the size of the output capacitance, output voltage and load current characteristic. a minimum soft-start capacitor can be estimated from: c ss > c out v out r sense (10 C4 [f/v s]) generally 0.1 m f is more than sufficient. overcurrent latchoff operation is not always needed or desired. load current is already limited during a short- circuit by the current foldback circuitry and latchoff opera- tion can prove annoying during troubleshooting. the feature can be overridden by adding a pull-up current greater than 5 m a to the run/ss pin. the additional current prevents the discharge of c ss during a fault and also shortens the soft-start period. using a resistor to v in as shown in figure 6a or 6c is simple, but slightly increases shutdown current. connecting a resistor to intv cc as shown in figure 6b and 6d eliminates the additional shutdown current, but requires a diode to isolate c ss . any pull-up network must be able to maintain run/ss above the 4.2v maximum latchoff threshold and overcome the 4 m a maximum discharge current. efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. although all dissipative elements in the circuit produce losses, four main sources account for most of the losses in ltc1909-8 circuits: 1. dc i 2 r losses. these arise from the resistances of the mosfets, inductor and pc board traces and cause the efficiency to drop at high output currents. in continuous mode the average output current flows through l, but is chopped between the top and bottom mosfets. if the two mosfets have approximately the same r ds(on) , then the resistance of one mosfet can simply be summed with the resistances of l and the board traces to obtain the dc i 2 r loss. for example, if r ds(on) = 0.01 w and r l = 0.005 w , the loss will range from 15mw to 1.5w as the output current varies from 1a to 10a. 2. transition loss. this loss arises from the brief amount of time the top mosfet spends in the saturated region during switch node transitions. it depends upon the input voltage, load current, driver strength and mosfet capacitance, among other factors. the loss is significant at input voltages above 20v and can be estimated from: transition loss @ (1.7a C1 ) v in 2 i out c rss f 3. intv cc current. this is the sum of the mosfet driver and control currents. this loss can be reduced by supply- ing intv cc current through the extv cc pin from a high efficiency source, such as an output derived boost net- work or alternate supply if available. 4. c in loss. the input capacitor has the difficult job of filtering the large rms input current to the regulator. it must have a very low esr to minimize the ac i 2 r loss and applicatio s i for atio wu uu 3.3v or 5v run/ss v in intv cc run/ss d1 (6a) (6b) d2* c ss r ss * c ss *optional to override overcurrent latchoff *optional to override overcurrent latchoff r ss * run/ss cpuon cpuon v in intv cc run/ss (6c) (6d) d2* c ss c ss r ss * r ss * 19098 f06 figure 6. run/ss pin interfacing with latchoff defeated
24 ltc1909-8 19098f sufficient capacitance to prevent the rms current from causing additional upstream losses in fuses or batteries. other losses, including c out esr loss, schottky diode d1 conduction loss during dead time and inductor core loss generally account for less than 2% additional loss. when making adjustments to improve efficiency, the input cur- rent is the best indicator of changes in efficiency. if you make a change and the input current decreases, then the efficiency has increased. if there is no change in input current, then there is no change in efficiency. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to d i load (esr), where esr is the effective series resistance of c out . d i load also begins to charge or discharge c out generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. the i th pin external components shown in figure 7 will provide adequate compensation for most applications. for a detailed explanation of switching con- trol loop theory see application note 76. design example as a design example, take a supply with the following specifications: v in = 7v to 24v (15v nominal), v out = 1.5v 100mv, i out(max) = 15a, f = 300khz. first, calculate the timing resistor with v on = v out : r khz pf k on = ()() = 1 300 10 330 and choose the inductor for about 40% ripple current at the maximum v in : l v khz a v v h = ()()() - ? ? ? ? =m 15 300 0 4 15 1 15 24 08 . . . . selecting a standard value of 1 m h results in a maximum ripple current of: d= () m () ? ? ? ? = i v khz h v v a l 15 300 1 1 15 24 47 . . . next, choose the synchronous mosfet switch. because of the narrow duty cycle and large current, a single so-8 mosfet will have difficulty dissipating the power lost in the switch. choosing two irf7811a (r ds(on) = 0.013 w , c rss = 60pf, q ja = 40 c/w) yields a nominal sense voltage of: v sns(nom) = (15a)(0.5)(1.3)(0.012 w ) = 117mv tying v rng to intv cc will set the current sense voltage range for a nominal value of 140mv with current limit occurring at 186mv. to check if the current limit is acceptable, assume a junction temperature of about 100 c above a 50 c ambient with r 150 c = 1.6: i mv aa limit 3 ()() w () + () = 186 05 16 0012 1 2 47 18 ... . and double check the assumed t j in the mosfet: p vv v a w bot = ? ? ? ? () w () = 24 1 5 24 21 7 2 16 0012 212 2 . . .. . t j = 50 c + (2.12w)(50 c/w) = 156 c because the top mosfet is on for such a short time, a single irf7811a will be sufficient. checking its power dissipation at current limit with r 90 c = 1.3: p v v a v a pf khz www bot = ()() w () + ()( )( )( )( ) =+= 15 24 21 7 1 3 0 012 1 7 24 21 7 60 300 046 038 084 2 2 . ... .. ... t j = 50 c + (0.84w)(50 c/w) = 92 c the junction temperatures will be significantly less at nominal current, but this analysis shows that careful attention to heat sinking will be necessary in this circuit. c in is chosen for an rms current rating of about 6a at temperature. the output capacitors are chosen for a low esr of 0.005 w to minimize output voltage changes due to applicatio s i for atio wu uu
25 ltc1909-8 19098f applicatio s i for atio wu uu inductor ripple current and load steps. the ripple voltage will be only: d v out(ripple) = d i l(max) (esr) = (4.7a) (0.005 w ) = 24mv however, a 0a to 15a load step will cause an output change of up to: d v out(step) = d i load (esr) = (15a) (0.005 w ) = 75mv the complete circuit is shown in figure 7. active voltage positioning active voltage positioning (also termed load deregula- tion or droop) describes a technique where the output voltage varies with load in a controlled manner. it is useful in applications where rapid load steps are the main cause of error in the output voltage. by positioning the output voltage above the regulation point at zero load, and below the regulation point at full load, one can use more of the error budget for the load step. this allows one to reduce the number of output capacitors by relaxing the esr requirement. in the design example, figure 7, five 0.025 w capacitors are required in parallel to keep the output voltage within tolerance. using active voltage positioning, the same specification can be met with only three capacitors. in this case, the load step will cause an output voltage change of: d= () ? ? ? ? w () = va mv out step () . 15 1 3 0 025 125 c c2 100pf c c1 470pf c ss 0.1 f c fb 100pf r on 330k sel sda scl vron r c 20k r f 1 19098 f07 r pg 100k 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 run/ss v on pgood v rng fcb i th sgnd i on v fb sel sda scl vron pgtmr boost tg sw sense + pgnd bg intv cc v in extv cc v cc gnd fb v osense cpuon c b 0.33 f m1 irf7811a d1 ups840 l1 1 h m2 irf7811a 2 d b cmdsh-3 c vcc 4.7 f c f 0.1 f c2 6.8nf c in 22 f 50v 3 v in 7v to 24v v out 1.5v 15a c out 270 f 2v 5 c in : united chemicon thcr70eih226zt c out : cornell dubilier esre271m02b l1: sumida cep125-ir0mc-h ltc1909-8 + 5v figure 7. cpu core voltage regulator 1.5v, 15a at 300khz
26 ltc1909-8 19098f by positioning the output voltage 60mv above the regula- tion point at no load, it will only drop 65mv below the regulation point after the load step, well within the 100mv tolerance. implementing active voltage positioning re- quires setting a precise gain between the sensed current and the output voltage. because of the variability of mosfet on-resistance, it is prudent to use a sense resis- tor with active voltage positioning. in order to minimize power lost in this resistor, a low value is chosen of 0.003 w . the nominal sense voltage will now be: v sns(nom) = (0.003 w )(15a) = 45mv to maintain a reasonable current limit, the voltage on the v rng pin is reduced to its minimum value of 0.5v, corre- sponding to a 50mv nominal sense voltage. next, the gain of the ltc1909-8 error amplifier must be determined. the change in i th voltage for a corresponding change in the output current is: d= ? ? ? ? d = () w ()() = i v v ri av th rng sense out 12 24 0 003 15 1 08 .. the corresponding change in the output voltage is deter- mined by the gain of the error amplifier and feedback divider. the ltc1909-8 error amplifier has a transconduc- tance g m that is constant over both temperature and a wide 40mv input range. thus, by connecting a load resistance r vp to the i th pin, the error amplifier gain can be precisely set for accurate active voltage positioning. d= ? ? ? ? d igr v v v th m vp out out 08 . solving for this resistance value: r vi vg v vv vms mv k vp out th m out = d d == (. ) (. )(. ) (. )(. )( ) . 08 15 108 08 17 125 953 the gain setting resistance r vp is implemented with two resistors, r vp1 connected from i th to ground and r vp2 connected from i th to intv cc . the parallel combination applicatio s i for atio wu uu of these resistors must equal r vp and their ratio deter- mines nominal value of the i th pin voltage when the error amplifier input is zero. to center the load line around the regulation point, the i th pin voltage must be set to correspond to half the output current. the relation be- tween i th voltage and the output current is: i v v ri i v v v aav v th nom rng sense out l () . . .... . = ? ? ? ? d ? ? ? ? + = ? ? ? ? w () ? ? ? ? + = 12 1 2 08 12 05 0 003 7 5 1 2 47 08 117 solving for the required values of the resistors: r v vi r v vv k k r v i r v v kk vp th nom vp vp th nom vp 1 2 5 5 5 5117 953 12 44 55 117 953 4073 == = === . . . . .. () () the modified circuit is shown in figure 8. figures 9 and 10 show the transient response without and with active voltage positioning. both circuits easily stay within 100mv of the 1.5v output. however, the circuit with active voltage positioning accomplishes this with only three output ca- pacitors rather than five. refer to design solutions 10 for additional information about active voltage positioning. smbus protocols the write word and read word protocols (figure 11) share three common features. first, the 7-bit slave ad- dress for both protocols is internally hardwired to 1110 001b = e2h. a single r/w bit follows the slave address. this bit is low for data transfer from the microprocessor to the ltc1909-8 and high for transfers in the opposite direction. second, the ltc1909-8 decodes only the three most significant bits of the 8-bit command code. table 3 shows the four valid combinations. all other combinations are ignored.
27 ltc1909-8 19098f applicatio s i for atio wu uu figure 9. normal transient response v out 100mv/div 1.5v i l 10a/div c out = 5 270 m f20 m s/div 3711 f09 v in = 15v figure 7 circuit figure 10. transient response with active voltage positioning v out 100mv/div 1.5v i l 10a/div c out = 3 270 m f20 m s/div 3711 f10 v in = 15v figure 8 circuit c c1 180pf c ss 0.1 f c fb 100pf r on 330k r f 1 19098 f08 r pg 100k r rng2 45.3k r rng1 4.99k r vp1 12.4k r vp2 40.2k 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 run/ss v on pgood v rng fcb i th sgnd i on v fb sel sda scl vron pgtmr boost tg sw sense + pgnd bg intv cc v in extv cc v cc gnd fb v osense cpuon c b 0.33 f m1 irf7811a d1 b540 l1 1 h m2 irf7811a 2 r sense 0.003 d b cmdsh-3 c vcc 4.7 f c f 0.1 f c in 22 f 50v 3 v in 7v to 24v v out 1.5v 15a c out 270 f 2v 5 c in : united chemicon thcr70eih226zt c out : cornell dubilier esre271m02b l1: sumida cep125-ir0mc-h ltc1909-8 + sel sda scl vron 5v figure 8. cpu core voltage regulator with active voltage positioning 1.5v/15a at 300khz
28 ltc1909-8 19098f applicatio s i for atio wu uu third, the data low and data high bytes correspond to registers 0 and 1 respectively. in write word protocol with c7 = c6 = 0, c5 = 1, the five most significant bits (vid0- vid4) of these bytes specify a resistor divider setting. table 3. ltc1909-8 command bits c7 c6 c5 command protocol 0 0 0 on write word 0 1 1 off write word 0 0 1 setup write word 0 1 0 read-back read word write word protocol each write word protocol (figure 11) begins with a start bit (s) and ends with a stop bit (p). as shown in the timing diagram the start and stop bits are defined as high-to-low and low-to-high sda transitions respectively, while scl is high. in between the start and stop bits, the microproces- sor transmits four bytes to the ltc1909-8. these are the address byte, an 8-bit command code and two data bytes. the ltc1909-8 samples each bit at the rising edges of the scl clock. when the microprocessor issues a start bit, all the slave devices on the bus, including the ltc1909-8 clock in the address byte, which consists of a 7-bit slave address and the r/w bit (set to 0). if the slave address from the microprocessor does not match the internal hardwired address, the ltc1909-8 returns to an idle state and waits for the next start bit. if the slave address matches, the ltc1909-8 acknowledges by pulling the sda line low for one clock cycle after the address byte. after detecting the acknowledgment bit (a), the microprocessor transmits the second byte or command code. the command code identifies the type of write word protocol as setup, on or off (table 3). the setup protocol is used to load two resistor divider settings into register 0 and 1. the on and off protocols turn the converters on or off in conjunction with the vron pin. once all 8 bits of the command code are clocked in, the ltc1909-8 issues a second acknowledgment bit to the microprocessor. after detecting the acknowledgment bit, the microproces- sor transmits two data bytes. figure 11. write word and read word protocols s 1110001 000xxxxx a don? care a don? care update dcon slave address on command data low (register 0) data high (register 1) a p s 1110001 011xxxxx a don? care a don? care update dcon slave address off command data low (register 0) data high (register 1) a p s 1110001 001xxxxx a vid4 vid3 vid2 vid1 vid0 x x x a a a a update dcon slave address setup command data high (register 1) data low (register 0) a p data low latched data high latched command latched vid4 vid3 vid2 vid1 vid0 x x x s 1110001 r/w r/w r/w r/w s 1110010 010xxxxx a vid4 vid3 vid2 vid1 vid0 0 0 rd a a a slave address read-back command data high (register 1) data low (register 0) a p data high loaded data low loaded stop (ignored) command latched dcon 00 dcon vid4 vid3 vid2 vid1 vid0 19098 f11
29 ltc1909-8 19098f applicatio s i for atio wu uu each data byte is acknowledged in turn for all three write word protocols but is only latched into register 0 or 1 in setup protocol. this prevents previously loaded settings from accidentally being changed. the first or data low byte is loaded into register 0. the second or data high byte is loaded into register 1. after issuing the final acknowledgment bit, the smbus interface returns to an idle state and waits for the next start bit. read word protocol the read word protocol starts off like write word proto- col but after the command code acknowledgment, the microprocessor issues a second start bit (called a re- peated start). this is followed by the slave address but with the r/w bit set high to indicate that data direction is now from the ltc1909-8 to the microprocessor. the ltc1909-8 then acknowledges the slave address and clocks the contents of register 0 (data low byte) to the micropro- cessor. the data low byte is acknowledged by the micro- processor. on detecting the acknowledgment bit, the ltc1909-8 clocks out the contents of register 1 (data high byte). as defined in the smbus specifications, the microprocessor does not acknowledge the last data byte. the ltc1909-8 enters an idle state to wait for the next start bit after clocking out the data high byte. the five most significant bits (vid0-vid4) of the data low and high bytes are the resistor divider settings previously loaded using the setup protocol. the next bit below the vid0- vid4 bits is the status of the dcon signal. if this bit is low (high), the dc/dc converters are switched on (off). the two unused, least significant bits of the data low and data high bytes are clocked out as zeros to eliminate the need to mask out these bits in software. operating sequence a typical control sequence for the ltc1909-8 is as follows: ? on power up, the dcon bit is preset to a high state by the power-on reset (por) circuit. the cpuon pin is pulled low to shut down the dc/dc converter. pgtmr and pgood pull low to indicate that the converters are not in regulation. ? pull vron low as a precaution. take sel high or low to select the divider setting; e.g., one that suits the existing power source (battery or wall-pack) or intended cpu speed. ? use the setup protocol to load the appropriate divider settings in registers 0 and 1 and enable the on/off state machine. ? use the read-back protocol to verify the contents of registers 0 and 1. ? repeat the setup and read-back if the codes are incor- rect (due to bus conflicts). ? send two on protocols in succession to clear the dcon bit. ? use the read-back protocol to verify that the dcon is low. a high state will indicate that an on command code was corrupted by bus conflicts. ? pull vron high. since dcon = 0, the cpuon pin enters a high impedance state, allowing the dc/dc converter to soft-start. pgtmr stays low for 50 m s. pgood stays low until the regulator output rises above the C7.5% regulation limit. ? to shut down the supply, send two off protocols to set the dcon bit high or pull vron low if immediate shutdown is required.
30 ltc1909-8 19098f pc board layout checklist when laying out a pc board follow one of the two sug- gested approaches. the simple pc board layout requires a dedicated ground plane layer. also, for higher currents, it is recommended to use a multilayer board to help with heat sinking power components. ? the ground layer should not have any traces and it should be as close as possible to the layer with power mosfets. ? place c in , c out , mosfets, d1 and inductor all in one compact area. it may help to have some components on the bottom side of the board. ? place ltc1909-8 chip with pins 20 to 28 facing the power components. keep the components connected to pins 16 to 18 close to ltc1909-8 (noise sensitive components). ? use an immediate via to connect the components to ground plane including sgnd, gnd and pgnd of ltc1909-8. use several bigger vias for power components. ? use compact plane for switch node (sw) to improve cooling of the mosfets and to keep emi down. ? use planes for v in and v out to maintain good voltage filtering and to keep power losses low. ? connect the v osense , fb and gnd pins of the resistor divider directly to the output of the dc/dc converter, the v fb pin and the sgnd pin of the controller. applicatio s i for atio wu uu ? flood all unused areas on all layers with copper. flood- ing with copper will reduce the temperature rise of power component. you can connect the copper areas to any dc net (v in , v out , gnd or to any other dc rail in your system). when laying out a printed circuit board, without a ground plane, use the following checklist to ensure proper opera- tion of the controller. these items are also illustrated in figure 12. ? segregate the signal and power grounds. all small- signal components should return to the sgnd pin at one point which is then tied to the pgnd pin close to the source of m2. tie the gnd pin directly to sgnd. ? place m2 as close to the controller as possible, keeping the pgnd, bg and sw traces short. ? connect the input capacitor(s) c in close to the power mosfets. this capacitor carries the mosfet ac current. ? keep the high dv/dt sw, boost and tg nodes away from sensitive small-signal nodes. ? connect the intv cc decoupling capacitor c vcc closely to the intv cc and pgnd pins. ? connect the top driver boost capacitor c b closely to the boost and sw pins. ? connect the v in pin decoupling capacitor c f closely to the v in and pgnd pins.
31 ltc1909-8 19098f c c2 bold lines indicate high current paths c c1 c ss c fb r on r c r f 19098 f12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 run/ss v on pgood v rng fcb i th sgnd i on v fb sel sda scl vron pgtmr boost tg sw sense + pgnd bg intv cc v in extv cc v cc gnd fb v osense cpuon c b m2 m1 d1 d b c f c vcc c out c in v in v out + + ltc1909-8 figure 12. ltc1909-8 pcb layout diagram applicatio s i for atio wu uu u package descriptio g package 28-lead plastic ssop (5.3mm) (reference ltc dwg # 05-08-1640) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. g28 ssop 0802 0.09 ?0.25 (.0035 ?.010) 0 ?8 0.55 ?0.95 (.022 ?.037) 5.00 ?5.60** (.197 ?.221) 7.40 ?8.20 (.291 ?.323) 1234 5 6 7 8 9 10 11 12 14 13 9.90 ?10.50* (.390 ?.413) 25 26 22 21 20 19 18 17 16 15 23 24 27 28 2.0 (.079) 0.05 (.002) 0.65 (.0256) bsc 0.22 ?0.38 (.009 ?.015) millimeters (inches) dimensions do not include mold flash. mold flash shall not exceed .152mm (.006") per side dimensions do not include interlead flash. interlead flash shall not exceed .254mm (.010") per side * ** note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale 0.42 0.03 0.65 bsc 5.3 ?5.7 7.8 ?8.2 recommended solder pad layout 1.25 0.12
32 ltc1909-8 19098f ? linear technology corporation 2001 lt/tp 0603 1k ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com related parts part number description comments ltc1380/ltc1393 multiplexer with smbus interface single-ended 8-channel/differential 4-channel analog mux ltc1622 550khz step-down controller 8-pin msop, synchronizable, soft-start; current mode ltc1623 smbus dual high side switch controller built-in charge pump drives n-channel mosfets, 8-lead msop package ltc1625/ltc1775 no r sense current mode synchronous step-down controller 97% efficiency; no sense resistor; 16-pin ssop ltc1628-sync dual, 2-phase synchronous step-down controller synchronizable 150khz to 300khz ltc1694/ltc1694-1 smbus accelerator thinsot tm , active pull-up improves data transmission and reliability, improves low state noise ltc1699-80 smbus vid programmer compliant with intel precision 0.35% resistor divider for use with 0.8v 5-bit mobile specifications referenced switching regulators ltc1699-81 smbus vid programmer compliant with intel precision 0.35% resistor divider for use with 0.8v desktop vrm8.4 specifications referenced switching regulators ltc1699-82 smbus vid programmer compliant with intel precision 0.35% resistor divider for use with 0.8v desktop vrm9.0 specifications referenced switching regulators ltc1709-7 high efficiency, 2-phase synchronous step-down controller up to 42a output; 0.925v v out 2v ltc1709-8 high efficiency, 2-phase synchronous step-down controller up to 42a output; vrm 8.4, 1.3v v out 3.5v ltc1710 smbus dual monolithic high side switch two integrated 0.4 w /300ma n-channel switches ltc1735 high efficiency, synchronous step-down controller burst mode operation; 16-pin narrow ssop; 3.5v v in 36v ltc1759 smbus interfaced smart battery charger constant current/constant voltage battery charger, up to 8a charge current, high efficiency synchronous charger ltc1772 thinsot step-down controller current mode; 550khz; very small solution size ltc1778 no r sense synchronous step-down controller no sense resistor required, 4v v in 36v, 0.8v v out (0.9) v in , gn16 lt ? 1786f smbus programmable ccfl switching regulator precision 100 m a full-scale dac, grounded lamp or floating lamp configurations ltc1876 2-phase, dual synchronous step-down controller with 3.5v v in 36v, power good output, 300khz operation step-up regulator ltc3701 dual, step-down controller current mode; 550khz; small 16-pin ssop, v in < 9.8v ltc3711 5-bit adjustable, wide operating range, no r sense gn24, mobile vid, 0.925v v out 2v step-down controller ltc3714 intel compatible, wide operating range, step-down controller g28, 0.6v v out 1.75v, programmable output with internal op amp offsets, 5-bit vid thinsot is a trademark of linear technology corporation.

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